reduced instruction

An improved testing method SOVM& series of verification method is proposed on the basis of the restricted thought for functional testing of microprocessor instruction decoding. It is clear that the length of testing sequence is reduced and the fault coverage is further increased.

提出了微处理器指令译码部分在受限验证思想下的一种改进测试方法&连环验证法，测试序列长度显著减少，故障覆盖率进一步提高。

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The use the single-chip reduced instruction set, instruction cycle clock are the number of CPU units.

该 单片机 采用精简指令集, 指令周期均以CPU时钟数为单位.

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ARM system structure inherits such characters of RISC ( Reduced Instruction Set Computer) as load/ store structure, fixed 32 bit instruction and format of three address instruction.

ARM体系结构继承了RISC结构的加载/存储体系结构、固定长32位指令和三地址指令格式等特性。

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Branch-delay is one of the RISC Reduced Instruction Set Computer technology characters.

延迟转移是RISC技术特点之一.

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Highly original reduced instruction set microprocessor designed by Inmos.

Inmos设计的独创的高度简化指令集微处理器.

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